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HD74CDC2509 3.3-v phase-lock loop clock driver preliminary 1st. edition december 1997 description the HD74CDC2509 is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. it uses a phase-lock loop (pll) to precisely align, in both frequency and phase, the feedback (fbout) output to the clock (clk) input signal. it is specifically designed for use with synchronous drams. the HD74CDC2509 operates at 3.3 v v cc and is designed to drive up to five clock loads per output. one bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of the input clock. output signal duty cycles are adjusted to 50 percent independent of the duty cycle at the input clock. each bank of outputs can be enabled or disabled separately via the control (1g and 2g) inputs. when the g inputs are high, the outputs switch in phase and frequency with clk; when the g inputs are low, the outputs are disabled to the logic-low state. unlike many products containing plls, the HD74CDC2509 does not require external rc networks. the loop filter for the pll is included on-chip, minimizing component count, board space, and cost. because it is based on pll circuitry, HD74CDC2509 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. this stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at clk, as well as following any changes to the pll reference or feedback signals. the pll can be bypassed for test purposes by strapping av cc to ground. features phase-lock loop clock distribution for synchronous dram applications external feedback (fbin) pin is used to synchronize the outputs to the clock input no external rc network required
HD74CDC2509 2 function table inputs outputs 1g 2g clk 1y (0:4) 2y (0:3) fbout xxlll l llhll h l hhl h h hl hhl h hhhhh h h : high level l : low level x : immaterial pin arrangement (top view) 15 16 17 18 19 20 21 22 23 24 v cc v cc av cc v cc v cc 1 2 3 4 5 6 7 8 9 10 11 12 agnd 1y0 1y1 1y2 gnd gnd 1y3 1y4 1g fbout clk 2y0 2y1 gnd gnd 2y2 2y3 13 14 2g fbin
HD74CDC2509 3 absolute maximum ratings item symbol ratings unit conditions supply voltage v cc C0.5 to 4.6 v input voltage *1 v i C0.5 to 6.5 v output voltage *1, 2 v o C0.5 to v cc +0.5 v input clamp current i ik C50 ma v i < 0 output clamp current i ok 50 ma v o < 0 or v o > v cc continuous output current i o 50 ma v o = 0 to v cc supply current i cc or i gnd 100 ma maximum power dissipation at ta = 55 c (in still air) *3 p t 0.7 w storage temperature t stg C65 to +150 c notes: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. the input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. 2. this value is limited to 4.6 v maximum. 3. the maximum package power dissipation is calculated using a junction temperature of 150 c and a board trace length of 750 mils. recommended operating conditions item symbol min typ max unit conditions supply voltage v cc 3.0 3.6 v input voltage v ih 2.0 v v il 0.8 v i 0v cc output current i oh C12 ma i ol 12 operating temperature t a 070 c note: unused inputs must be held high or low to prevent them from floating.
HD74CDC2509 4 logic diagram 11 1g 1y0 3 1y1 4 pll 1y2 5 1y3 8 1y4 9 14 2g 24 clk 13 fbin av 23 cc 2y0 21 2y1 20 2y2 17 2y3 16 fbout 12
HD74CDC2509 5 pin function pin name no. type description clk 24 i clock input. clk provides the clock signal to be distributed by the HD74CDC2509 clock driver. clk is used to provide the reference signal to the integrated pll that generates the clock output signals. clk must have a fixed frequency and fixed phase for the pll to obtain phase lock. once the circuit is powered up and a valid clk signal is applied, a stabilization time is required for the pll to phase lock the feedback signal to its reference signal. fbin 13 i feedback input. fbin provides the feedback signal to the internal pll. fbin must be hard-wired to fbout to complete the pll. the integrated pll synchronizes clk and fbin so that there is nominally zero phase error between clk and fbin. 1g 11 i output bank enable. 1g is the output enable for outputs 1y(0:4). when 1g is low, outputs 1y(0:4)are disabled to a logic-low state. when 1g is high, all outputs 1y(0:4) are enabled and switch at the same frequency as clk. 2g 14 i output bank enable. 2g is the output enable for outputs 2y(0:3). when 2g is low, outputs 2y(0:3)are disabled to a logic low state. when 2g is high, all outputs 2y(0:3) are enabled and switch at the same frequency as clk. fbout 12 o feedback output. fbout is dedicated for external feedback. it switches at the same frequency as clk. when externally wired to fbin, fbout completes the feedback loop of the pll. 1y(0:4) 3, 4, 5, 8, 9 o clock outputs. these outputs provide low-skew copies of clk. output bank 1y(0:4) is enabled via the 1g input. these outputs can be disabled to a logic low state by deasserting the 1g control input. 2y(0:3) 16, 17, 20, 21 o clock outputs. these outputs provide low-skew copies of clk. output bank 2y(0:3) is enabled via the 2g input. these outputs can be disabled to a logic low state by deasserting the 2g control input. av cc 23 power analog power supply. av cc provides the power reference for the analog circuitry. in addition, av cc can be used to bypass the pll for test purposes. when av cc is strapped to ground, pll is bypassed and clk is buffered directly to the device outputs. agnd 1 ground analog ground. agnd provides the ground reference for the analog circuitry. v cc 2, 10, 15, 22 power power supply gnd 6, 7, 18,19 ground ground
HD74CDC2509 6 electrical characteristics item symbol min typ *1 max unit test conditions input clamp voltage v ik C1.2 v v cc = 3 v, i i = C18 ma output voltage v oh v cc C0.2 v v cc = min to max, i oh = C100 m a 2.1 v cc = 3 v, i oh = C12 ma 2.4 v cc = 3 v, i oh = C6 ma v ol 0.2 v cc = min to max, i ol = 100 m a 0.8 v cc = 3 v, i ol = 12 ma 0.55 v cc = 3 v, i ol = 6 ma input current i in 5 m av cc = 3.6 v, v in = v cc or gnd quiescent supply current i cc 10 m av cc = 3.6 v, v i = v cc or gnd, i o = 0, outputs: l or h d i cc 500 m av cc = 3.3 to 3.6 v, one input at v cc C0.6 v, other inputs at v cc or gnd input capacitance c in 4pfv cc = 3.3 v, v i = v cc or gnd output capacitance c o 6pfv cc = 3.3 v, v o = v cc or gnd note: 1. for conditions shown as min or max, use the appropriate value specified under recommended operating conditions.
HD74CDC2509 7 switching characteristics (c l = 30 pf) item symbol v cc = 3.3 v 0.165 v v cc = 3.3 v 0.3 v unit from (input) to (output) min typ max min typ max phase error time t pe -0.7~0.1 ns 66 mhz < clkin - < 100 mhz fbin - phase error time C jitter *2 C500 C50 C310 ps clkin - =100 mhz fbin - between output pins skew *1 t sk (o) 200 ps any y or fbout any y or fbout jitter C100 100 ps f (clkin > 66 mhz) any y or fbout duty cycle 45 55 % f (clkin 66 mhz) any y or fbout 43 55 f (clkin > 66 mhz) any y or fbout output rise / fall time t tlh 1.3 1.9 0.8 2.1 ns any y or fbout t thl 1.7 2.3 1.2 2.5 any y or fbout notes: the specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed. 1. the t sk(o) specification is only valid for equal loading of all outputs. 2. phase error does not include jitter. the total phase error is C600 ps to +50 ps for the 5% v cc range. timing requirements item symbol min max unit test conditions input clock frequency f clock 25 125 mhz input clock duty cycle 40 60 % stabilization time *1 1 ms after power up note: 1. time required for the integrated pll circuit to obtain phase lock of its feedback signal to its reference signal. in order for phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at clk. until phase lock is obtained, the specifications for propagation delay and skew parameters given in the switching characteristics table are not applicable.
HD74CDC2509 8 test circuit 500 w from output under test c = 30 pf l *1 note: 1. c l includes probe and jig capacitance. waveforms C 1 plh t v oh v ol cc 0 v 3 v 50% v cc 50% v cc 50% v 2 v 2 v 0.4 v 0.4 v tlh t thl t input output (=fbout) notes: 1. all input pulses are supplied by generators having the following characteristics: prr 100 mhz, z o = 50 w , t r = 1.2 ns, t f = 1.2 ns. 2. the outputs are measured one at a time with one transition per measurement.
HD74CDC2509 9 waveforms C 2 phase error t clkin fbin sk (o) t fbout any y sk (o) t any y any y
HD74CDC2509 10 package dimensions unit : mm 0.13 m 0.65 112 24 13 7.80 4.4 8.10 max 0.5 0.1 0 ?8 0.17 0.05 6.4 0.2 0.10 1.10 max 0.65 max 0.22 +0.08 ?.07 0.07 +0.03 ?.04 1.0 hitachi code jedec code eiaj code weight ttp-24db ? ? 0.08 g 0.20 0.06 0.15 0.04
HD74CDC2509 11 when using this document, keep the following in mind: 1. this document may, wholly or partially, be subject to change without notice. 2. all rights are reserved: no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without hitachis permission. 3. hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the users unit according to this document. 4. circuitry and other examples described herein are meant merely to indicate the characteristics and performance of hitachis semiconductor products. hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. no license is granted by implication or otherwise under any patents or other rights of any third party or hitachi, ltd. 6. medical applications: hitachis products are not authorized for use in medical applications without the written consent of the appropriate officer of hitachis sales company. such use includes, but is not limited to, use in life support systems. buyers of hitachis products are requested to notify the relevant hitachi sales offices when planning to use the products in medical applications. hitachi, ltd. semiconductor & ic div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 for further information write to: hitachi america, ltd. semiconductor & ic div. 2000 sierra point parkway brisbane, ca. 94005-1835 u s a tel: 415-589-8300 fax: 415-583-4207 hitachi europe gmbh electronic components group continental europe dornacher stra? 3 d-85622 feldkirchen m?nchen tel: 089-9 91 80-0 fax: 089-9 29 30 00 hitachi europe ltd. electronic components div. northern europe headquarters whitebrook park lower cookham road maidenhead berkshire sl6 8ya united kingdom tel: 01628-585000 fax: 01628-585160 hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 hitachi asia (hong kong) ltd. unit 706, north tower, world finance centre, harbour city, canton road tsim sha tsui, kowloon hong kong tel: 27359218 fax: 27306071 copyright ?hitachi, ltd., 1997. all rights reserved. printed in japan.

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